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ds05-50102-2e fujitsu semiconductor data sheet embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc. mcp (multi-chip package) flash memory cmos 8m ( 8/ 16) flash memory & 8m ( 8/ 16) flash memory mb84vb2000 -10 /mb84vb2001 -10 n features ? contain 2 chips of mbm29lv800a, and each chip have separate ce . ? power supply voltage of 2.7 to 3.6 v ? high performance 100 ns maximum access time ? operating temperature C40 to +85 c ? minimum 100,000 write/erase cycles ? sector erase architecture one 16 k byte, two 8 k bytes, one 32 k byte, and fifteen 64 k bytes 2 chips any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture mb84vb2000: top sector mb84vb2001: bottom sector ? embedded erase tm algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ?low v cc write inhibit 2.5 v ? erase suspend/resume suspends the erase operation to allow a read data in another sector within the same device ? please refer to "mbm29lv800ta/ba" data sheet in detailed function
2 mb84vb2000 -10 /mb84vb2001 -10 n block diagram v ss v cc 8 m bit reset flash memory we 8 m bit flash memory ce 1 a 0 to a 18 oe v ss v cc dq 0 to dq 15 ry/by a -1 ce 2 byte
3 mb84vb2000 -10 /mb84vb2001 -10 n connection diagram (top view) abcdef gh 6n.c. v ss dq 1 a 1 a 2 a 4 n.c. a 9 5a 10 dq 5 dq 2 a 0 a 3 a 7 ry/by a 14 4oe dq 7 dq 4 dq 0 a 6 a 18 reset a 15 3a 11 a 8 a 5 dq 8 dq 3 dq 12 a 12 byte 2a 13 a 17 ce 2 ce 1 dq 10 v cc dq 6 dq 15 /a -1 1we n.c. a 16 v ss dq 9 dq 11 dq 13 dq 14 table 1 mb84vb2000/mb84vb2001 pin configuration pin function input/ output a -1 , a 0 to a 18 address inputs (common) i dq 0 to dq 15 data inputs/outputs (common) i/o ce 1 chip enable 1 i ce 2 chip enable 2 i oe output enable (common) i we write enable (common) i ry/by ready/busy outputs (common) o reset hardware reset pin/sector protection unlock (common) i byte selects 8-bit or 16-bit mode (common) i n.c. no internal connection v ss device ground (common) power v cc device power supply (common) power
4 mb84vb2000 -10 /mb84vb2001 -10 n product line up n logic symbol part no. mb84vb2000/mb84vb2001 ordering part no. v cc = 3.0 v -10 max. address access time (ns) 100 max. ce access time (ns) 100 max. oe access time (ns) 40 table 2 mb84vb2000/mb84vb2001 user bus operations (byte = v ih ) operation (5) ce 1 ce 2 oe we a 0 a 1 a 6 a 9 dq 0 to dq 15 reset auto-select manufactures code (1) hl lhlllv id code h lh auto-select device code (1) hl lhhllv id code h lh read (3) hl lha 0 a 1 a 6 a 9 d out h lh full standby hhxxxxxx high-z h output disable xxhhxxxx high-z h write (program/erase) hl hla 0 a 1 a 6 a 9 d in h lh enable sector protection (2), (4) hl v id lhlv id xh lh verify sector protection (2), (4) hl lhlhlv id code h lh temporary sector unprotection xxxxxxxx x v id reset (hardware)/standby xxxxxxxx high-z l +0.6 v C0.3 v
5 mb84vb2000 -10 /mb84vb2001 -10 legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. notes: 1.manufacturer and device codes may also be accessed via a command register write sequence. see table 7. 2.refer to the section on sector protection. 3.we can be v il if oe is v il , oe at v ih initiates the write operations. 4.v cc = 3.3 v 10% 5.do not apply ce 1 = ce 2 = v il at a time. table 3 mb84vb2000/mb84vb2001 user bus operations (byte = v il ) operation (5) ce 1 ce 2 oe we dq 15 / a -1 a 0 a 1 a 6 a 9 dq 0 to dq 7 reset auto-select manufactures code (1) hl lhllllv id code h lh auto-select device code (1) hl lhlhllv id code h lh read (3) hl lha -1 a 0 a 1 a 6 a 9 d out h lh full standby h h x x x x x x x high-z h output disable x x h h x x x x x high-z h write (program/erase) hl hla -1 a 0 a 1 a 6 a 9 d in h lh enable sector protection (2), (4) hl v id llhlv id xh lh verify sector protection (2), (4) hl lhl lhlv id code h lh temporary sector unprotection xxxxxxxxx x v id reset (hardware)/standby x x x x x x x x x high-z l
6 mb84vb2000 -10 /mb84vb2001 -10 n flexible sector-erase architecture ? one 16 k byte, two 8 k bytes, one 32 k byte, and fifteen 64 k bytes 2. ? individual-sector, multiple-sector, or bulk-erase capability. mb84vb2000 sector architecture mb84vb2001 sector architecture 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 60000h 58000h 50000h 48000h 40000h 38000h 30000h 16k byte/8k word 8k byte/4k word 8k byte/4k word 32k byte/16k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 7ffffh 7e000h 7d000h 7c000h 78000h 70000h 68000h 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 64k byte/32k word 32k byte/16k word 8k byte/4k word 8k byte/4k word 16k byte/8k word 28000h 20000h 18000h 10000h 08000h 00000h 48000h 40000h 38000h 30000h 28000h 20000h 18000h 7ffffh 78000h 70000h 68000h 60000h 58000h 50000h 10000h 08000h 04000h 03000h 02000h 00000h c0000h b0000h a0000h 90000h 80000h 70000h 60000h fffffh fc000h fa000h f8000h f0000h e0000h d0000h 50000h 40000h 30000h 20000h 10000h 00000h 90000h 80000h 70000h 60000h 50000h 40000h 30000h fffffh f0000h e0000h d0000h c0000h b0000h a0000h 20000h 10000h 08000h 06000h 04000h 00000h ( 8) ( 16) ( 8) ( 16)
7 mb84vb2000 -10 /mb84vb2001 -10 n functional description table 4 sector address tables (mb84vb2000) sector address a 18 a 17 a 16 a 15 a 14 a 13 a 12 address range ( 8) address range ( 16) sa0 0 0 0 0 x x x 00000h to 0ffffh 00000h to 07fffh sa1 0 0 0 1 x x x 10000h to 1ffffh 08000h to 0ffffh sa2 0 0 1 0 x x x 20000h to 2ffffh 10000h to 17fffh sa3 0 0 1 1 x x x 30000h to 3ffffh 18000h to 1ffffh sa4 0 1 0 0 x x x 40000h to 4ffffh 20000h to 27fffh sa5 0 1 0 1 x x x 50000h to 5ffffh 28000h to 2ffffh sa6 0 1 1 0 x x x 60000h to 6ffffh 30000h to 37fffh sa7 0 1 1 1 x x x 70000h to 7ffffh 38000h to 3ffffh sa8 1 0 0 0 x x x 80000h to 8ffffh 40000h to 47fffh sa9 1 0 0 1 x x x 90000h to 9ffffh 48000h to 4ffffh sa10 1 0 1 0 x x x a0000h to affffh 50000h to 57fffh sa11 1 0 1 1 x x x b0000h to bffffh 58000h to 5ffffh sa12 1 1 0 0 x x x c0000h to cffffh 60000h to 67fffh sa13 1 1 0 1 x x x d0000h to dffffh 68000h to 6ffffh sa14 1 1 1 0 x x x e0000h to effffh 70000h to 77fffh sa15 1 1 1 1 0 x x f0000h to f7fffh 78000h to 7bfffh sa16 1 1 1 1 1 0 0 f8000h to f9fffh 7c000h to 7cfffh sa17 1 1 1 1 1 0 1 fa000h to fbfffh 7d000h to 7dfffh sa18 1 1 1 1 1 1 x fc000h to fffffh 7e000h to 7ffffh
8 mb84vb2000 -10 /mb84vb2001 -10 table 5 sector address tables (mb84vb2001) sector address a 18 a 17 a 16 a 15 a 14 a 13 a 12 address range ( 8) address range ( 16) sa0 0 0 0 0 0 0 x 00000h to 03fffh 00000h to 01fffh sa1 0 0 0 0 0 1 0 04000h to 05fffh 02000h to 02fffh sa2 0 0 0 0 0 1 1 06000h to 07fffh 03000h to 03fffh sa3 0 0 0 0 1 x x 08000h to 0ffffh 04000h to 07fffh sa4 0 0 0 1 x x x 10000h to 1ffffh 08000h to 0ffffh sa5 0 0 1 0 x x x 20000h to 2ffffh 10000h to 17fffh sa6 0 0 1 1 x x x 30000h to 3ffffh 18000h to 1ffffh sa7 0 1 0 0 x x x 40000h to 4ffffh 20000h to 27fffh sa8 0 1 0 1 x x x 50000h to 5ffffh 28000h to 2ffffh sa9 0 1 1 0 x x x 60000h to 6ffffh 30000h to 37fffh sa10 0 1 1 1 x x x 70000h to 7ffffh 38000h to 3ffffh sa11 1 0 0 0 x x x 80000h to 8ffffh 40000h to 47fffh sa12 1 0 0 1 x x x 90000h to 9ffffh 48000h to 4ffffh sa13 1 0 1 0 x x x a0000h to affffh 50000h to 57fffh sa14 1 0 1 1 x x x b0000h to bffffh 58000h to 5ffffh sa15 1 1 0 0 x x x c0000h to cffffh 60000h to 67fffh sa16 1 1 0 1 x x x d0000h to dffffh 68000h to 6ffffh sa17 1 1 1 0 x x x e0000h to effffh 70000h to 77fffh sa18 1 1 1 1 x x x f0000h to fffffh 78000h to 7ffffh
9 mb84vb2000 -10 /mb84vb2001 -10 *1: a -1 is for byte mode. (b): byte mode (w): word mode table 6.1 flash memory autoselect codes type a 6 a 1 a 0 a -1 *1 code (hex) manufactures code v il v il v il v il 04h device code mb84vb2000 byte v il v il v ih v il dah word x 22dah mb84vb2001 byte v il v il v ih v il 5bh word x 225bh table 6.2 expanded autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufactures code 04h a -1 /0000000000000100 device code mb84vb2000 (b) dah a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 1 1 0 1 1 0 1 0 (w) 22dah0010001011011010 mb84vb2001 (b) 5bh a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 0 1 0 1 1 0 1 1 (w) 225bh0010001001011011
10 mb84vb2000 -10 /mb84vb2001 -10 address bits a 11 to a 17 = x = h or l for all address commands except or program address (pa) and sector address (sa). bus operations are defined in tables 2 and 3. the system should generate the following address patterns: word mode: 555h or 2aah to addresses a 0 to a 10 byte mode: aaah or 555h to addresses a -1 and a 0 to a 10 both read/reset commands are functionally equivalent, resetting the device to the read mode. ra =address of the memory location to be read pa =address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa =address of the sector to be erased. the combination of a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. rd =data read from location ra during read operation. pd =data to be programmed at location pa. data is latched on the falling edge of write pulse. spa:sector address to be protected. set sector address (sa) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd:sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. table 7 flash memory command definitions command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1xxxhf0h read/reset 3 555h aah 2aah 55h 555h f0hrard aaah 555h aaah autoselect 3 555h aah 2aah 55h 555h 90h aaah 555h aaah program 4 555h aah 2aah 55h 555h a0hpapd aaah 555h aaah chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h aaah 555h aaah aaah 555h aaah sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h aaah 555h aaah aaah 555h sector erase suspend erase can be suspended during sector erase with addr. (h or l). data (b0h) sector erase resume erase can be resumed after suspend with addr. (h or l). data (30h) set to fast mode 3 555h aah 2aah 55h 555h 20h aaah 555h aaah fast program (note) 2 xxxh a0hpapd xxxh reset from fast mode (note) 2 xxxh 90h xxxh f0h xxxh xxxh extended sector protect 4 xxxh 60h spa 60h spa 40h spa sd
11 mb84vb2000 -10 /mb84vb2001 -10 n absolute maximum ratings storage temperature .................................................................................................. C55c to + 125c ambient temperature with power applied .................................................................. C25c to +85c voltage with respect to ground all pins (note) .......................................................... C0.3 v to v cc + 0.5 v v cc f/v cc s supply (note) .............................................................................................. C0.3 v to +4.6 v note: minimum dc voltage on input or i/o pins are C0.5 v. during voltage transitions, inputs may negative overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins are v cc f + 0.5 v or v cc s + 0.5 v. during voltage transitions, outputs may positive overshoot to v cc + 2.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating ranges commercial devices ambient temperature (t a ) .........................................................................C40c to +85c v cc supply voltages ..................................................................................+2.7 v to +3.6 v operating ranges define those limits between which the functionality of the device is guaranteed. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand.
12 mb84vb2000 -10 /mb84vb2001 -10 n dc characteristics notes: 1.the i cc current listed includes both the dc operating current and the frequency dependent component (at 10 mhz). 2.i cc active while embedded algorithm (program or erase) is in progress. 3. automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. (v id C v cc ) do not exceed 9 v. 5. total power consumption is (condition of flash 1) + (condition of flash 2). parameter symbol parameter description test conditions min. max. unit i li input leakage current v in = v ss to v cc , v cc = v cc max. C1.0 +1.0 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max. C1.0 +1.0 m a i lit a 9 , oe , reset inputs leakage current v cc = v cc max. a 9 , oe , reset = 12.5 v 70 m a i cc1 v cc active current (note 1, 5) ce = v il , oe = v ih , f = 10 mhz byte 22 ma word 25 ce = v il , oe = v ih , f = 5 mhz byte 12 ma word 15 i cc2 v cc active current (note 2, 5) ce = v il , oe = v ih 35ma i cc3 v cc current (standby) (note 5) v cc = v cc max., ce = v cc 0.3 v, reset = v cc 0.3 v 5 m a i cc4 v cc current (standby, reset) (note 5) v cc = v cc max., reset = v ss 0.3 v 5 m a i cc5 v cc current (automatic sleep mode) (note 3, 5) v cc = v cc max., ce = v ss 0.3 v, reset = v cc 0.3 v v in = v cc 0.3 v or v ss 0.3 v 5a v il input low level C0.5 0.6 v v ih input high level 2.0 v cc + 0.3 v v id voltage for autoselect and sector protection (a 9 , oe , reset ) (note 4) 11.5 12.5 v v ol output low voltage level i ol = 4.0 ma, v cc = v cc min. 0.45 v v oh1 output high voltage level i oh = C2.0 ma, v cc = v cc min. 2.4 v v oh2 i oh = C100 m a, v cc = v cc min. v cc C 0.4 v v lko low v cc lock-out voltage 2.3 2.5 v
13 mb84vb2000 -10 /mb84vb2001 -10 n ac characteristics ?ce timing ? read only operations characteristics note: test conditionsCoutput load: 1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level input: 1.5 v output: 1.5 v parameter symbols description test setup -10 unit jedec standard t ccr ce recover time min. 0 ns parameter symbols description test setup -10 (note) unit jedec standard min. max. t avav t rc read cycle time 100 ns t avqv t acc address to output delay ce = v il oe = v il 100ns t elqv t ce chip enable to output delay oe = v il 100ns t glqv t oe output enable to output delay 40 ns t ehqz t df chip enable to output high-z 30 ns t ghqz t df output enable to output high-z 30 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first 0ns t ready reset pin low to read mode 20 s t elfl t elfh ce or byte switching low or high 5 ns
14 mb84vb2000 -10 /mb84vb2001 -10 ? erase/program operations notes: 1. this does not include the preprogramming time. 2. this timing is for sector protection operation. parameter symbols description -10 unit jedec standard min. typ. max. t avav t wc write cycle time 100 ns t avwl t as address setup time (we to addr.) 0 ns t avel t as address setup time (ce to addr.) 0 ns t wlax t ah address hold time (we to addr.) 50 ns t elax t ah address hold time (ce to addr.) 50 ns t dvwh t ds data setup time 50 ns t whdx t dh data hold time 0 ns t oes output enable setup time 0 ns t oeh output enable hold time read 0 ns toggle and data polling 10 ns t ghel t ghel read recover time before write (oe to ce )0ns t ghwl t ghwl read recover time before write (oe to we )0ns t wlel t ws we setup time (ce to we )0ns t elwl t cs ce setup time (we to ce )0ns t ehwh t wh we hold time (ce to we )0ns t wheh t ch ce hold time (we to ce )0ns t wlwh t wp write pulse width 50 ns t eleh t cp ce pulse width 50 ns t whwl t wph write pulse width high 30 ns t ehel t cph ce pulse width high 30 ns t whwh1 t whwh1 byte programming operation 8 s t whwh2 t whwh2 sector erase operation (note 1) 1 15 sec t vcs v cc setup time 50 s t vidr rise time to v id (note 2) 500 ns t vlht voltage transition time (note 2) 4 s t wpp write pulse width (note 2) 100 s t oesp oe setup time to we active (note 2) 4 s t csp ce setup time to we active (note 2) 4 s t rb recover time from ry/by 0ns t rp reset pulse width 500 ns t rh reset hold time before read 200 ns t eoe delay time from embedded output enable 100 ns t busy program/erase valid to ry/by delay 90 ns t flqz byte switching low to output high-z 30 ns t flqv byte switching high to output active 30 ns
15 mb84vb2000 -10 /mb84vb2001 -10 n switching waveforms ce 1 t ccr t ccr ce 2 figure 1 timing diagram for alternating flash to flash
16 mb84vb2000 -10 /mb84vb2001 -10 we oe ce t ce t oe dq addresses stable high-z output valid high-z t oeh t acc t rc reset t acc t oh dq t rc addresses stable high-z output valid t rh t df figure 2 ac waveforms for read operations addresses addresses
17 mb84vb2000 -10 /mb84vb2001 -10 t ch t wp t whwh1 t wc t ah ce oe t rc addresses data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out notes: 1.pa is address of the memory location to be programmed. 2.pd is data to be programmed at byte address. 3.dq 7 is the output of the complement of the data written to the device. 4.d out is the output of the data written to the device. 5.figure indicates last two bus cycles out of four bus cycle sequence. 6.these waveforms are for the 16 mode. (the addresses differ from 8 mode.) figure 3 alternate we controlled program operation timings we oe ce data polling dq 7
18 mb84vb2000 -10 /mb84vb2001 -10 ce oe we t cp t whwh1 t wc t ah addresses data t as t cph t dh dq 7 a0h d out 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd t ds notes: 1.pa is address of the memory location to be programmed. 2.pd is data to be programmed at byte address. 3.dq 7 is the output of the complement of the data written to the device. 4.d out is the output of the data written to the device. 5.figure indicates last two bus cycles out of four bus cycle sequence. 6.these waveforms are for the 16 mode. (the addresses differ from 8 mode.) figure 4 alternate ce controlled program operation timings data polling dq 7 ce oe we
19 mb84vb2000 -10 /mb84vb2001 -10 v cc addresses data t wp 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc 55h 55h 80h aah aah 10h/ 30h ce oe we * : sa is the sector address for sector erase. addresses = 555h (word), aaah (byte) for chip erase. note: these waveforms are for the 16 mode. (the addresses differ from 8 mode.) figure 5 ac waveforms chip/sector erase operations we oe ce
20 mb84vb2000 -10 /mb84vb2001 -10 t oeh t oe t whwh1 or 2 t eoe data t df t ch t ce high-z high-z dq 7 = valid data dq 0 to dq 6 valid data * dq 7 dq 0 to dq 6 data dq 0 to dq 6 = output flag ce oe we dq 7 * : dq 7 = valid data (the device has completed the embedded operation.) figure 6 ac waveforms for data polling during embedded algorithm operations we oe ce dq 7 oe we ce t oeh dq 6 data dq 6 = toggle dq 6 = toggle dq 6 = stop toggling valid * t oe t oes * : dq 6 stops toggling.(the device has completed the embedded operation.) figure 7 ac waveforms for toggle bit during embedded algorithm operations oe we ce
21 mb84vb2000 -10 /mb84vb2001 -10 ry/by we ce the rising edge of the last we signal t busy entire programming or erase operations figure 8 ry/by timing diagram during write/erase operations we ce the rising edge of the last we signal ry/by reset we t rp t ready t rb figure 9 reset , ry/by timing diagram reset we
22 mb84vb2000 -10 /mb84vb2001 -10 ce byte t elfh t fhqv a -1 data output (dq 0 to dq 7 ) dq 15 dq 15 /a -1 dq 0 to dq 14 (dq 0 to dq 14 ) data output figure 10 timing diagram for word mode configuration ce byte dq 15 /a -1 dq 0 to dq 14 t elfl dq 15 a -1 t flqz data output (dq 0 to dq 7 ) (dq 0 to dq 14 ) data output figure 11 timing diagram for byte mode configuration the falling edge of the last we signal t hold ce or we (t ah ) t set (t as ) input valid byte figure 12 byte timing diagram for write operations
23 mb84vb2000 -10 /mb84vb2001 -10 ce we oe t vlht sax a 18 , a 17 , a 16 a 15 , a 14 a 13 , a 12 say a 0 a 6 a 9 12 v 3 v t vlht 12 v 3 v t vlht t vlht t oesp t wpp t csp t oe 01h data v cc a 1 t vcs sax : sector address for initial sector say : sector address for next sector note: a -1 is v il on byte mode. figure 13 ac waveforms for sector protection timing diagram we oe ce
24 mb84vb2000 -10 /mb84vb2001 -10 figure 14 extended sector protection algorithm to sector protection yes no no plscnt = 1 no yes protection other sector start sector protection extended sector plscnt = 25? device failed remove v id from reset completed remove v id from reset write reset command write reset command reset = v id wait to 4 m s protection entry? to setup sector protection write xxxh/60h write spa/60h (a 0 = v il , a 1 = v ih , a 6 = v il ) time out 150 m s to verify sector protection write spa/40h (a 0 = v il , a 1 = v ih , a 6 = v il ) data = 01h? ? device is operating in temporary sector read from sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) increment plscnt setup next sector address no yes yes unprotection mode fast mode algorithm
25 mb84vb2000 -10 /mb84vb2001 -10 ry/by we reset ce 12 v 3 v v cc t vlht program or erase command sequence 3 v t vlht t vcs t vidr t vlht figure 15 temporary sector unprotection timing diagram we reset ce ry/by toggle dq 2 and dq 6 with oe we dq 2 dq 6 erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete note: dq 2 is read from the erase-suspended sector. figure 16 dq 2 vs dq 6 we toggle dq2 and dq6 with oe
26 mb84vb2000 -10 /mb84vb2001 -10 n erase and programming performance n pin capacitance note: test conditions t a = 25c, f = 1.0 mhz n handling of package please hadle this package carefully since the sides of package are right angle. parameter limits unit comments min. typ. max. sector erase time 1 15 sec excludes programming time prior to erasure word programming time 16 5,200 m s excludes system-level overhead byte programming time 8 3,600 m s chip programming time (1m byte) 8.450sec excludes system-level overhead erase/program cycle 100,000 cycles parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 tbd tbd pf c out output capacitance v out = 0 tbd tbd pf c in2 control pin capacitance v in = 0 tbd tbd pf
27 mb84vb2000 -10 /mb84vb2001 -10 n pac k ag e n package dimensions 48-pin plastic fbga (bga-48p-m06) c 1998 fujitsu limited mcm-m001-2-3 10.00?.15 0.30?.10 (.012?004) 1.40?.20 (.055?008) 5.00?.15 (.197?006) (.394?006) 0.40?.10 (.016?004) 1.00?.15 (.039?006) 7.00?.15(.276?006) 0.15(.006) 11.00?.15(.433?006) index 1st pin index dimension in mm (inches). 48-pin plastic bga (bga-48p-m06) note: the actual shape of corners may differ from the dimension.
28 mb84vb2000 -10 /mb84vb2001 -10 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: (044) 754-3763 fax: (044) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9804 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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